debugging - VHDL Code for Binary Division bug -

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I have written the code for a binary dividend that takes in 8 bit dividend, 3 bit divisor, and 5 bit quotient ( 3 bit balance) I have spent hours trying to fix a bug that gives wrong results but I did not recognize it. Any help would be greatly appreciated! I basically get the wrong answer for my inputs, but I do not understand why a bus is taking the values ​​and on the first clock cycle where there is St 1, the dividend register is filled. After the second clock cycle, the separator register is loaded and calculated for the next three clock chakras.

The V signal indicates that an overflow has occurred (the result can not be fit in five pieces of the quotient), my sign is the starting signal to start the process, for registering shifts Shift is the signal, subtraction is subtractor for subtraction signal. 

  Library IEEE; Use IEEE.STD_LOGIC_1164.all; IEEE.STD_LOGIC_ARITH.all; Use; Use IEEE.STD_LOGIC_UNSIGNED.all; Unit dividers port (bus_in: std_logic_vector (8 down down); cents, clerk, reset: std_logic in; quantitative: out std_logic_vector (4 down to 0); remaining: out std_logic_vector (2 down from 0); v: out std_logic ); End divider; The behavior of the architectural separator is the signal state, next location: integer range 0 to 5; Signal C, LD1, LD2, SU, SH: Study_logic; Signal separator: std_logic_vector (down to 2); Signal pane: std_logic_vector (3 down down 0); Signal dividend: std_logic_vector (8 down down); Start Subout & LT; = Dividend (8 Down Down 5) - ('0' and Separator); C & lt; = Not Subout (3); Remaining & lt; = Dividend (7 to 5 down); Quotient & lt; = Dividend (4 down to 0); State_graph: Process (state, ct, c) ld1 and lt; = '0' starts; LD2 & lt; = '0'; V & lt; = '0'; Sh & lt; = '0'; Su & ​​lt; = '0'; Case condition is when 0 = & gt; If (cents = '1') then LD1 & lt; = '1'; NextState & lt; = 1; Second front sitel & lt; = 0; end if; When 1 = & gt; If (cents = '1') then LD2 & lt; = '1'; NextState & lt; = 2; Other Ld2 & lt; = '1'; NextState & lt; = 2; end if; When 2 = & gt; If (C = '1') then we'll see the value of V & lt; = '1'; NextState & lt; = 0; Otherwise S & lt; = '1'; NextState & lt; = 3; end if; When 3 4 = & gt; If (C = '1') then it is   
 This is the picture that shows the divisor and dividend loading correctly my registers so I think the issue is with the actual division code I state machine properly Is working from   
 
 
 are invented not write the wheel again myself.  
 Either  q  
 
 Write or use the IP core from your FPGA vendor.

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