Generate ports in VHDL? -

Is there a way to generate port announcements in VHDL? I would like to do something similar to #IFDEF for debug signals for pins for an oscope, in this way I can enable or disable debug logic immediately. For example:

  is the unit my_entity port (debug_label: if debug_on generates 1 debug 1: out; and debug_label; ....); End component;  

When I try to do something like that, it does not work. Is there any way to do this work? Or is there an alternative way of doing something?

The port may not be conditional, but for example std_logic_vector via normal mode Can be configurable from, and length can also be 0, which results in zero range. It is showing that there is a unit:

  unit MDL is normal (DEBUG_LEN: natural: = 0); Port (... debug_o: out std_logic_vector (DEBUG_LEN - 1 below from 0)); End unit;  

You should run a select synthesis how your selected synthesis tool handles the null range while specifying the body.